一种低功耗无电容型LDO的设计  

Design of a Low Power Capacitor-Free Low Dropout Regulator

作　　者：王晋雄[1] 原义栋[1] 张海峰[1] 

机构地区：[1]中国电力科学研究院通信与用电技术分公司,北京100192

出　　处：《半导体技术》2011年第4期316-321,共6页Semiconductor Technology

摘　　要：提出了一种片上集成的低功耗无电容型LDO（low drop out）电路。该电路采用折叠型eascode运放作为误差放大器，通过消除零点的密勒补偿技术提高了环路稳定性；并在电路中加入了一种新的限流保护结构以保证输出电流过大时对LDO的输出进行保护。此外，在电路中加入了省电模式，可在保持LDO输出1．8V情况下节省大于70％的功耗。该设计采用HHNEC0．13μmCMOS工艺，仿真结果显示：在2．5～5．5V电源供电、各个工艺角及温度变化条件下，LDO输出的线性调整率小于2．3mV／V，负载调整率小于14μV／mA，温度系数小于27×10^-6／℃；在正常工作模式下，整个LDO消耗85μA电流；在省电模式下仅消耗23斗A电流。A full on chip low power capacitor-free low drop out regulator was presented. Folded cascade Amplifier was chosen as the error amplifier, the miller compensation technology was used to cancel right-half-plane zero so as to improve the circuit loop stability. A new current limit topology was proposed to protect the LDO output in case of over current. Besides that, standby mode was employed in the LDO circuit, which can save more than 70% power consumption while keeping the LDO output voltage at 1.8 V. The chip was fabricated in HHNEC 0. 13 μm CMOS technology. The simulation results demonstrate that the line regulation is less than 2.3 mV/V, load regulation is less than 14μV/mA, and temperature coefficient is below 27×10^-6/℃ over all process corner and the temperature range under the power supply of 2.5 - 5.5 V. The total LDO circuit consumes 85μA in active mode while 23 μA in standby mode.

关 键 词：密勒补偿 限流保护 省电模式 低功耗 

分 类 号：TN432[电子电信—微电子学与固体电子学]