基于FPGA的实时中值滤波器硬件实现  

Design of real-time median filter based on FPGA

作　　者：王莉[1] 苏光大[1] 

机构地区：[1]清华大学电子工程系,北京100084

出　　处：《电子技术应用》2011年第4期58-60,共3页Application of Electronic Technique

摘　　要：针对高清图像在中值滤波预处理过程中排序量多、速度慢的特点,提出适合邻域图像并行处理机的分块存储方法。在流水线结构下,1个时钟周期可以并行处理32个3×3邻域的中值滤波运算,实现了高速、实时的1 920×1 080灰度图像中值滤波器。Aiming at the characteristics of median filter that high quantity sort and low speed in high definition pre-processing, this paper introduces block storage method in neighborhood image parallel procesor, and in pipeline structure , one clock cycle can parallelly run 32 times 3×3 median filter operation.The system can implement median filter with 1 920×1 080 size quickly and real-timely.

关 键 词：高清视频监控 中值滤波器 邻域图像并行处理机 FIFO 

分 类 号：TN911.73[电子电信—通信与信息系统]