基于层次结构的高端容错体系结构研究与设计  

Research and design of high end fault-tolerant architecture based on hierarchical structure

作　　者：杨耀红[1] 

机构地区：[1]中国国土资源经济研究院,北京101149

出　　处：《计算机工程与设计》2011年第4期1347-1350,共4页Computer Engineering and Design

摘　　要：针对当前容错技术软硬件耦合度大、可靠性差的特点,通过对计算机故障的分析,利用成熟的路径冗余技术I、P组播技术、内核容错等相关技术,提出了基于层次结构的高端容错体系结构设计模型,真正实现软件与硬件的无缝融合。该模型对整个高端容错体系结构划分为3个层级、分别是芯片级、操作系统级、应用级,并对这3个层次进行详细的论述。最后通过马尔科夫状态图表明该模型是高可靠并切实可行的。With reference to the strong coupling degree and poor reliability of the current hardware and software of fault-tolerant tech-nology based on the analysis of computer failure,the hierarchy based on high end fault-tolerant architecture design model is presented by using sophisticated path redundancy,IP multicast technology,the fault-tolerant kernel and other related technologies.It truly im-plements seamless integration of software and hardware.The model of entire high end fault-tolerant architecture is divided into three levels,chip-level,operating system level,application-level as well as the three levels of detail.The final adoption of Markov state diagram proves that the model is highly reliable and feasible.

关 键 词：EPIC体系结构 高端容错 节点控制器 路径冗余 IP组播 

分 类 号：TP303[自动化与计算机技术—计算机系统结构]