Wearout Tolerant Network Processing on Asymmetric Multi-core Processor  

作　　者：Peter D. Ungsunan LIN Chuang KONG Xiangzhen 

机构地区：[1]Department of Computer Science and Technology, Tsinghua University, Beijing 100084, China

出　　处：《Chinese Journal of Electronics》2011年第1期35-38,共4页电子学报（英文版）

摘　　要：As transistors get smaller and approach technological limits, they suffer from increased susceptibility to failures due to wearout. Future multi-core processors will have many cores, but with decreased service life due to manufacturing variability and high operating temperatures from high power densities. This poses a problem as complex systems with many less reliable cores operate at high temperatures over time, and a small failure can yield unpredictable results in software. However, for network processing applications, processor wearout failure can be mitigated in a gracefully degradable way by taking advantage of the predictable and fault tolerant nature of packet processing. A fault-tolerant asymmetric core arrangement is proposed to improve overall system dependability, useful life and performance, and a SPN model used to predict performability. System throughput and availability is predicted under various loads, as well as long term packet processing behavior.

关 键 词：Asymmetric multi-core Performability Wearout tolerance. 

分 类 号：TP316[自动化与计算机技术—计算机软件与理论] TS933.5[自动化与计算机技术—计算机科学与技术]