Floating-Point FPGA Gaussian Elimination in Reconfigurable Computing System  

作　　者：ZHANG Bowei GU Guochang SUN Lin WU Yanxia 

机构地区：[1]College of Computer Science and Technology, Harbin Engineering University, Harbin 150001, China

出　　处：《Chinese Journal of Electronics》2011年第1期51-54,共4页电子学报（英文版）

摘　　要：This paper presents a hardware-optimized variant of the well-known Gaussian elimination and its IEEE-754 single-precision FPGA implementation with highly efflcient design, which is worked as an Application function unit （AFU） in a loosely-coupled reconfigurable computing prototype system. In this design, pipelined floating-point operators are employed supported by opensource FPLibrary. The design is mainly composed of uniformly distributed entries, yielding a standalone worst case runtime of O（n2） opposed to O（n3） of the software replication. The results indicate that 15 times-speedup is achieved comparing to the software run by a 2.6GHz Pentium4 CPU with 1GB main memory. To evaluate the hardware, a simple model of reconfigurable system has also been proposed using a Xilinx ML555 board which connects and communicates with a desktop computer via the PCIe port. DMA access method is used for data block transport between host and AFU. To the best of authors＇ knowledge, there is no efficient floating-point FPGA for solving Linear systems of equations （LSEs） in the previous work.

关 键 词：Gaussian elimination FLOATING-POINT Reconflgurable computing 

分 类 号：TP338[自动化与计算机技术—计算机系统结构] TP312[自动化与计算机技术—计算机科学与技术]