基于FPGA的DES掩码算法硬件设计与实现  

Hardware Design and Implementation of DES Masking Algorithm Based on FPGA Platform

作　　者：王创伟[1] 丁国良[1] 尹文龙[1] 常小龙[1] 

机构地区：[1]军械工程学院计算机工程系,河北石家庄050003

出　　处：《计算机技术与发展》2011年第4期160-163,共4页Computer Technology and Development

基　　金：国家高技术研究发展计划(863)(2007AA01Z454)

摘　　要：随着FPGA芯片在安全领域上的广泛应用,有关FPGA密码芯片的抗DPA研究也越来越受关注,但目前的研究成果大多针对智能卡的安全防护。针对功耗分析技术的特点及关键技术,特别是DPA技术进行研究,提出了具体的改进防御方法。使用硬件描述语言VHDL在现场可编程门阵列(FPGA)上实现具备加密/解密功能的DES核,采用掩码方法对DES硬件结构进行改进,通过仿真和实验进行功能验证,改进的加密算法结构性能符合要求,在理论上具有抗DPA攻击的能力。With the widespread application of FPGA circuit in security field,the DPA-resistant research of FPGA cipher chip is getting much more attention.But most of the present research focus on security of smart card.Aimed at the characteristic of power attack technology and critical technology,especially DPA,to propose improved specify defend approach.By using the VHDL,implement a DES core which has encode/decode function based on FPGA.After applying the masking technique on FPGA,improve the DES hardware structures.It was validated by simulation and experiment.The results show that the design satisfys the demand which has the ability of the DPA resistance in theory.

关 键 词：现场可编程门阵列 数据加密标准 差分功耗分析 掩码 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]