A 6.25 Gbps CMOS 10 B/8 B decoder with pipelined architecture  

作　　者：张小伟 胡庆生 

机构地区：[1]Institute of RF- & OE-ICs,Southeast University

出　　处：《Journal of Semiconductors》2011年第4期145-148,共4页半导体学报（英文版）

基　　金：Project supported by the National High Technology Research and Development Program of China(No2006AA01Z239)

摘　　要：A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μm2.Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps.At a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.A fully pipelined 10 B/8 B decoder is presented with shorter critical path than before,and so its speed is improved greatly.Based on the proposed architecture,a 10 B/8 B decoder is implemented based on standard cells in 0.18μm CMOS technology with a core area of 375×375μm2.Measurement results show that the decoder works well and its speed can be up to 6.25 Gbps.At a 1.8 V power supply,the total power consumption is 21.6 mW during 6.25 Gbps operation and the peak-to-peak jitter in the eye diagram is 177.8 ps.

关 键 词：SERDES 10 B/8 B decoder PIPELINED HIGH-SPEED 

分 类 号：TN764[电子电信—电路与系统]