A 270-MHz to 1.5-GHz CMOS PLL clock generator with reconfigurable multi-functions for FPGA  

作　　者：张辉 杨海钢 王瑜 刘飞 高同强 

机构地区：[1]Institute of Electronics,Chinese Academy of Sciences [2]Graduate University of the Chinese Academy of Sciences [3]Institute of Electronics,Chinese Academy of Sciences,Beijing 100190,China

出　　处：《Journal of Semiconductors》2011年第4期149-154,共6页半导体学报（英文版）

基　　金：Project supported by the National High Technology Research and Development Program of China(No2008AA010701)

摘　　要：A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.A PLL clock generator with reconfigurable multi-functions for FPGA design applications is presented. This clock generator has two configurable operation modes to achieve clock multiplication and phase alignment functions,respectively.The output clock signal has advanced clock shift ability such that the phase shift and duty cycle are programmable.In order to further improve the accuracy of phase alignment and phase shift,a VCO design based on a novel quick start-up technique is proposed.A new delay partition method is also adopted to improve the speed of the post-scale counter,which is used to realize the programmable phase shift and duty cycle.A prototype chip implemented in a 0.13-μm CMOS process achieves a wide tuning range from 270 MHz to 1.5 GHz.The power consumption and the measured RMS jitter at 1 GHz are less than 18 mW and 9 ps,respectively.The settling time is approximately 2μs.

关 键 词：PLL clock generator RECONFIGURABLE VCO 

分 类 号：TN432[电子电信—微电子学与固体电子学]