基于FPGA的提高延时精度和范围的方法  

FPGA-Based Approach to Improve the Delay of Accuracy and Range

作　　者：左治方[1] 李跃华[1] 高玉良[1] 杨振强[1] 

机构地区：[1]空军雷达学院,湖北武汉430019

出　　处：《电气电子教学学报》2009年第B11期41-43,共3页Journal of Electrical and Electronic Education

摘　　要：为了提高延时的精度和范围，解决两者之间的矛盾，本文提出了一种利用不同时钟之间的相位关系提高延时精度的方法。该方法首先利用FPGA中锁相环将同一参考时钟进行移相形成具有不同相位信息的一组时钟，然后将这些具有不同相位关系的时钟作为一种特殊的Gray码计数器的输入来实现延时的精细计数，然后通过采用粗延时和精延时相结合的方法增加了延时的范围。本文最后用FPGA对该方法进行了实现，实验结果表明该方法具有在时钟频率一定的前提下，有效提高延时精度和范围的特点，有效的解决了延时精度和范围的矛盾。In order to improve the delay of accuracy and range, In this paper, a method is proposed. In this method, the reference clock was phase-shifted by phase shifter in order to get a number of clocks with different phase and then these clocks have been used as input signals of a Special Gray code counter, which took full advantage of all the phase information of clocks to improve the accuracy of the delay. Finally, a test was carried out and the experimental results show that the method is effective to improve the accuracy and extent of delay and solves the conflict between accuracy and scope of the delay.

关 键 词：锁相环 相移 格雷码计数器 FPGA 

分 类 号：TN791[电子电信—电路与系统]