H.264/AVC整数DCT变换与量化的FPGA实现  

FPGA Implementation of Integer DCT Transform and Quantization for H.264/AVC

作　　者：郁光珍[1] 郑博[1] 李松亭[1] 赵不贿[1] 

机构地区：[1]江苏大学电气信息工程学院,江苏镇江212013

出　　处：《电视技术》2011年第9期20-22,共3页Video Engineering

基　　金：江苏大学研究生创新计划项目(CX09B_15XZ)

摘　　要：根据H.264/AVC的变换量化原理,在FPGA上设计并实现了整数变换及量化部分。首先采用层次化、模块化的思想,将系统划分为多个功能模块,降低了硬件实现的复杂度,对DCT算法进行了优化,并对量化模块采用了流水线操作,最后设计全部采用Verilog硬件描述语言实现,并用Modelsim进行功能仿真,同时实验结果通过在Xilinx公司Vertex2P系列的XC2VP30 FPGA上验证。仿真及综合结果表明,与优化之前相比,系统所需时钟周期减少了29个,最大时钟频率可达到135.498MHz,为H.264标准的硬件实现提供了参考。According to the principle of transform and quantization of H.264/AVC, the design and implementation of integer transform and quantization part based on FPGA are presented. Firstly, with hierarchy and modularization idea, the system is divided into some function modules, which can reduce the complexity of hardware implementation. In the design, the DCT algorithms are optimized and the quantization module is adopted pipelining. The whole design is implemented by Verilog HDL, simulated in Modelsim and verified in Xilinx Vertex2P XC2VP30 FPGA. The synthesis result indicates that compared with unoptimizable system the clock period reduces of 29 and the maximum clock frequency reaches 135.498 MHz, providing a reference for H.264 hardware implementation.

关 键 词：H.264 DCT 量化 FPGA 

分 类 号：TN919.81[电子电信—通信与信息系统]