一种低复杂度RS编码器的FPGA实现  

Implement of a Low Complexity RS Encoder on FPGA

作　　者：付兴[1] 樊孝明[1] 

机构地区：[1]桂林电子科技大学信息与通信学院,广西桂林541004

出　　处：《电视技术》2011年第9期50-53,共4页Video Engineering

摘　　要：提出了一种新的基于标准基的有限域并行常系数乘法器结构,使用该结构设计了低复杂度的RS(204,188)编码器。该编码器由15个常系数乘法器构成。每个常系数乘法器通过共享一些相同硬件操作,使得编码器中异或门XOR的数目减少了30%左右。最后在FPGA上实现了该编码电路,并用QuartusⅡ7.2自带的SignalTap逻辑分析仪进行了片上验证。结果表明,与以往的RS编码器相比,该编码器具有速度快和占用硬件资源少的特点。A new structure of parallel constant multiplier for finite field based on the standard basis is proposed. A low complexity RS （204,188） encoder is designed using the structure. The encoder is constructed by 15 constant multipliers, which share the same hardware operations. As a result, the number of XOR gates of the whole eneoder reduces about 30%. The encoder circuit on FPGA is implemented, and the circuit using SignalTap logic analyzer on Quartus II 7.2 is verified. The result indicates that the RS encoder is featured with high speed and low hardware complexity compared with other RS eneoders.

关 键 词：RS编码 常系数乘法器 FPGA 

分 类 号：TN911.22[电子电信—通信与信息系统]