基于CPLD/FPGA的多串口设计与实现  

Design and implementation of multi-serial port based on CPLD/FPGA

作　　者：粟慧龙[1] 肖辽亮[1] 

机构地区：[1]湖南铁道职业技术学院,湖南株洲412001

出　　处：《电子设计工程》2011年第7期77-80,共4页Electronic Design Engineering

摘　　要：在工业控制中如何提高一对多的串口通讯可靠性和系统的集成性成为研究热点。本文利用嵌入式技术,提出基于CPLD/FPGA的多串口扩展设计方案。实现并行口到多个全双工异步通讯口之间的转换,并根据嵌入式系统实时性的需要,在每个UART接收器中开辟了8个接收缓冲单元,实现高速嵌入式CPU与RS232通讯设备之间的速度匹配,同时,串行口波特率等参数可根据需要进行设置。通过实践证明,本文设计的基于CPLD/FPGA的多串口完全符合工业控制中一对多串口通讯的要求。How to improve the reliability of multi-serial port communication and the integration of system becomes one of central issues in industrial control. By using embedded technic, this article proposed one multi-serial port expansion program based on CPLD/FPGA. To achieve the conversion from the parallel port to multiple full-duplex asynchronous communication port, it opens up 8 receiving buffer units in each UART receiver according to the real-time needs of embedded systems. It can implement the speed matching of high-speed embedded CPU and RS232 communication devices. At the same time, the serial port baud rate can be set to achieve the needs of different communication baud. Through the practice it proves that the design of multi-serial port based on CPLD/FPGA can fully meet the requirements of the one-to-many communication in industrial control.

关 键 词：CPLD/FPGA 多串口扩展 全双工 异步通信 嵌入式系统 

分 类 号：TN492[电子电信—微电子学与固体电子学]