提升小波高速分解的系统设计与实现  

Design and Implementation of High-speed Decomposition for Wavelet Lifting System

作　　者：杨扬[1] 邓家先[1] 吴昊[1] 

机构地区：[1]海南大学信息科学与技术学院,海南海口570228

出　　处：《通信技术》2011年第4期16-18,共3页Communications Technology

摘　　要：为了解决小波变换在图像实时处理系统中的瓶颈问题,提出了一种硬件实现9/7整形小波高速变换的方法。该方法使用新的小波变换结构和小波变换基,采用一种基于行列同时变换的多级同时变换方式,即进行多级同时变换,且每一级的行列变换也同时进行。使用现场可编程逻辑门阵列(FPGA,Field Programmable Gate Array)的IP核实现片内缓存,降低了设计的复杂度,实现了图像的高速分解。整个设计采用VHDL对算法完成建模和实现,综合和仿真结果表明,该系统占用的资源少,分解速度很快,实现了高速的图像数据流输出,可应用到图像压缩的很多领域。In order to solve the wavelet transform bottleneck in the real-time image processing system,a method for the hardware implementation of 9/7 integer wavelet transform is proposed,which employs the new structure of wavelet transform and the new wavelet base.This method realizes the multi-level transform based on the row-column transform at the same time,this means carrying out the multi-level transform while doing the row-column transform of each level.IP Core of FPGA is used to achieve chip memory,thus to reduce the design complexity and achieve the high speed decomposition of the image.The modeling and realization are achieved by VHDL.The experimental results show that this scheme occupies less hardware resources,and with high-speed decomposition,achieves the high-speed image data stream output.So this system is applicable to many areas of image compression.

关 键 词：9/7整形小波 多级同时 行列同时 现场可编程门阵列 

分 类 号：TN911.73[电子电信—通信与信息系统]