Op Amp共享与移除取样保持电路之低功率管线式ADC芯片设计  

Design of Low Power Pipelined ADC Chips with Op Amp Sharing and SHA-less

作　　者：黄进芳 林伟健[1] 刘荣宜 

机构地区：[1]国立台湾科技大学电子工程系,台湾台北10672 [2]中华电信研究所,台湾桃园32617

出　　处：《山东科技大学学报（自然科学版）》2011年第2期70-79,共10页Journal of Shandong University of Science and Technology(Natural Science)

摘　　要：以TSMC0.18μmCMOS制程实现10位元(10-bit)、每秒取样2×107次、操作电压1.8 V的管线式(pipe-line)模拟数字转换器(ADC)芯片。本设计主要是使用1.5-bit/stage架构,并且配合运算放大器(op amp)共享(sharing)技术,拔除传统第一级取样保持放大器(SHA,sample and hold amplifier)以节省功耗。此芯片的量测结果为输入信号频率2 MHz时,输出的SNDR与ENOB各为46.2 dB与7.32-bit,包含焊线垫片(pad)的芯片面积为1.54(1.391×1.107)mm2,芯片功耗为29.2 mW。A 10-bit 20 MS/s pipelined analog-to-digital converter（ADC） with a 1.8 V voltage supply was designed and successfully fabricated with TSMC 0.18 μm CMOS process.In this chip design,a conventional 1.5-bit/stage network with the operational amplifier（op amp） sharing approach was adopted and the sample-and-hold amplifier（SHA） circuit in the first stage used in the conventional chip design was removed.The overall measured results show that with the input frequency of 2 MHz,the SNDR and ENOB are 46.2 dB and 7.32-bit,respectively.The total chip power consumption is 29.2 mW and chip area is 1.54（1.391×1.107） mm2 including pads.

关 键 词：模拟数字转换器 管线式 运算放大器共享 

分 类 号：TN792[电子电信—电路与系统]