高频率、低成本的SHA-256算法VLSI实现  

Implementation of the SHA-256 Hash Function of a High-Frequency and Low-Cost VLSI

作　　者：应建华[1] 罗柳平[1] 

机构地区：[1]华中科技大学电子科学与技术系,湖北武汉430074

出　　处：《微电子学与计算机》2011年第5期28-31,共4页Microelectronics & Computer

摘　　要：SHA-256安全散列算法广泛应用于数据完整性校验及数字签名等领域.为满足安全SoC系统对SHA-256高工作频率和低硬件成本的设计需求,提出了一种新颖的SHA-256 VLSI实现方法,通过分解算法实现步骤,进而缩短关键路径,节省硬件资源.采用SMIC 0.13μm CMOS工艺综合实现,结果表明其最高工作频率达334.5MHz,资源消耗减少了70%.The secure hash algorithm of SHA-256 is widely met in the fields of data integrity and digital signature authentication.A novel VLSI architecture of SHA-256 is presented to achieve the goal of high frequency and low cost of secure SoC.The optimized design shortens the critical path and reduces hardware resource by decomposing steps of the algorithm.Synthesized with SMIC 0.13CMOS technology,the result indicates that the proposed implementation delivers 334.5MHz of maximal requency and 70% of area cost reduction.

关 键 词：SHA-256算法 VLSI实现 关键路径 面积优化 

分 类 号：TP31[自动化与计算机技术—计算机软件与理论]