CMOS门电路电磁信息泄漏评估  

The Electromagnetic Information Leakage Evaluation on Basic CMOS Gate

作　　者：丁国良[1] 常小龙[1] 陈家文[1] 武翠霞[2] 

机构地区：[1]军械工程学院计算机工程系,河北石家庄050003 [2]河北工业大学,天津300130

出　　处：《微电子学与计算机》2011年第5期67-70,共4页Microelectronics & Computer

基　　金：国家"八六三"计划项目(2007AA01Z454)

摘　　要：通过将CMOS工艺中的导线转化为电偶极子模型,提出了一种对CMOS工艺的门电路进行电磁信息泄漏评估的方法.仿真实验采用TSMC0.18μm工艺,实现了基于单轨逻辑以及SABL双轨逻辑的与非门,并用提出的评估方法对门电路的电磁信息泄漏进行评估.仿真结果表明,该评估方法能够对CMOS门电路的电磁信息泄漏程度进行量化评估,同时还表明了双轨门电路电磁信息泄漏弱于单轨门电路.A method of evaluating electromagnetic information leakage of the CMOS gate circuit was presented by changing the lead in CMOS technology into dipole model.The simulation adopted TSMC0.18 μm process technology,and implemented the NAND gate based single rail logic and SABL double rail logic,meanwhile,the electromagnetic information leakage was evaluated by the given method.The results showed that this method was able to quantitative evaluate the electromagnetic information leakage of the CMOS gate,and that the electromagnetic information leakage of double rail logic gate was much weaker than single logic gate.

关 键 词：电磁信息泄漏 差分电磁分析 电偶极子模型 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]