一种应用于电荷泵锁相环的高性能鉴频鉴相器  

A CMOS Phase Frequency Detector of High Performance for Charge Pump Phase Locked Loop

作　　者：孙鹏[1] 徐元旭[1] 姚恩义[1] 胡永双[1] 

机构地区：[1]哈尔滨工业大学微电子科学与技术系,哈尔滨150006

出　　处：《微处理机》2011年第1期41-44,共4页Microprocessors

摘　　要：鉴频鉴相器是电荷泵锁相环中的一个重要模块,它的死区、速度、鉴相范围、鉴相灵敏度等因素影响整个锁相环的性能,其中死区和速度是两个非常重要但相互矛盾的技术指标。本设计为一种预充电型鉴频鉴相器,采用了TSMC 0.18μm RF CMOS工艺,利用Agilent公司推出的系统分析软件ADS(Advanced Design System)完成对电路的仿真。仿真结果表明鉴频鉴相器鉴相灵敏度好,速度快,鉴相死区仅为5ps,很好地解决了速度与死区之间的矛盾。Phase Frequency Detector is an important component of Charge-Pump Phase-locked Loop and some aspects of Phase Frequency Detector affect the performance of PLL such as dead zone,speed,phase detecting range,phase sensitivity and so on.Based on these considerations,a precharge Phase Frequency Detector is designed.The design is based on TSMC 0.18μm RF CMOS technology.The simulation results with ADS show good phase detecting character and high fast operation speed,the dead zone is only about 5ps.

关 键 词：CMOS 电荷泵锁相环 鉴频鉴相器 死区 速度 

分 类 号：TN492[电子电信—微电子学与固体电子学]