Characterization analysis of UDSM LVTSCR under TLP stress  

作　　者：李立 刘红侠 董翠 周文 

机构地区：[1]Key Laboratory for Wide Band Gap Semiconductor Materials and Devices of Ministry of Education,School of Microelectronics,Xidian University [2]School of Science,Xidian University

出　　处：《Journal of Semiconductors》2011年第5期42-47,共6页半导体学报（英文版）

基　　金：Project supported by the National Natural Science Foundation of China(Nos.60976068,60936005);the Cultivation Fund of the Key Scientific and Technical Innovation Project,Ministry of Education of China(No.708083).

摘　　要：The characteristics of a low-voltage triggering silicon-controlled rectifier （LVTSCR） under a transmission line pulse （TLP） and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge （ESD） design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron （UDSM） LVTSCR structure under ESD stress and the improvement of TLP test technology.The characteristics of a low-voltage triggering silicon-controlled rectifier （LVTSCR） under a transmission line pulse （TLP） and the characteristics of high frequency are analyzed. The research results show that the anode series resistance has a significant effect on the key points of the snapback curve. The device characteristics can fit the requirements of a electrostatic discharge （ESD） design window by adjusting the anode series resistance. Furthermore, the set-up time of the ESD has an influence on the turn-on voltage of the LVTSCR. A steep rising edge will cause the turn-on voltage to increase. The parasitic capacitance of the device for different voltage biases and frequencies determines the capacitive impedance, and its accuracy calculation is very important to the ESD design of high frequency circuits. Our research results provide a theoretical basis for the design of an ultra-deep sub-micron （UDSM） LVTSCR structure under ESD stress and the improvement of TLP test technology.

关 键 词：ultra-deep sub-micron electrostatic discharge transmission line pulse low-voltage triggering silieoncontrolled rectifier 

分 类 号：TN35[电子电信—物理电子学]