Partitioning the Conventional DBT System for Multiprocessors  

作　　者：马汝辉 管海兵 朱二周 杨洪波 杨吟冬 梁阿磊 

机构地区：[1]Shanghai Key Laboratory of Scalable Computing and Systems,Department of Computer Science and Engineering Shanghai Jiao Tong University

出　　处：《Journal of Computer Science & Technology》2011年第3期474-490,共17页计算机科学技术学报（英文版）

基　　金：supported by the National Natural Science Foundation of China under Grant Nos. 60970108,60970107;the Scienceand Technology Commission of Shanghai Municipality under Grant Nos. 09510701600,10DZ1500200,10511500102;IBM SUR Funding;IBM Research-China JP Funding

摘　　要：Noticeable performance improvement via ever-increasing transistors is gradually trapped into a predicament since software cannot logically and efficiently utilize hardware resource, such as multi-core resource. This is an inevitable problem in dynamic binary translation （DBT） system as well. Though special purpose hardware as aide tool, through some interfaces, provided by DBT enables the system to achieve higher performance, the limitation of it is significant, that is, it is impossible to be used widely by another one. To overcome this drawback, we focus on building compatible software architecture to acquire higher performance without platform dependence. In this paper, we propose a novel multithreaded architecture for DBT system through partitioning distinct function module, which is to adequately utilize multiprocessors resource. This new architecture devides couples the common DBT system （DBTs） working routine into dynamic translation, optimization, and translated code execution phases, and then ramifies them into different threads to enable them concurrently executed. In this new architecture, several efficient novel methods are presented to cope with intractable work that puzzles most researchers, such as communication mechanism, cache layout, and mutual exclusion between threads. Experimental results using SPECint 2000 indicate that this new architecture for DBT system can achieve higher performance -- speed up the traditional DBT system by about average 10.75%, with better CPU utilization.Noticeable performance improvement via ever-increasing transistors is gradually trapped into a predicament since software cannot logically and efficiently utilize hardware resource, such as multi-core resource. This is an inevitable problem in dynamic binary translation （DBT） system as well. Though special purpose hardware as aide tool, through some interfaces, provided by DBT enables the system to achieve higher performance, the limitation of it is significant, that is, it is impossible to be used widely by another one. To overcome this drawback, we focus on building compatible software architecture to acquire higher performance without platform dependence. In this paper, we propose a novel multithreaded architecture for DBT system through partitioning distinct function module, which is to adequately utilize multiprocessors resource. This new architecture devides couples the common DBT system （DBTs） working routine into dynamic translation, optimization, and translated code execution phases, and then ramifies them into different threads to enable them concurrently executed. In this new architecture, several efficient novel methods are presented to cope with intractable work that puzzles most researchers, such as communication mechanism, cache layout, and mutual exclusion between threads. Experimental results using SPECint 2000 indicate that this new architecture for DBT system can achieve higher performance -- speed up the traditional DBT system by about average 10.75%, with better CPU utilization.

关 键 词：DBT OPTIMIZATION MICROPROCESSOR MULTI-CORE SPECint 2000 

分 类 号：TP332[自动化与计算机技术—计算机系统结构]