Physical Implementation of the Eight-Core Godson-3B Microprocessor  

作　　者：王茹 范宝峡 杨梁 高燕萍 刘动 肖斌 王江嵋 张译夫 王宏 胡伟武 

机构地区：[1]Institute of Computing Technology,Chinese Academy of Sciences [2]Graduate School of Chinese Academy of Sciences [3]Loongson Technologies Corporation Limited

出　　处：《Journal of Computer Science & Technology》2011年第3期520-527,共8页计算机科学技术学报（英文版）

基　　金：supported by the Important National Science and Technology Specific Projects under Grant Nos. 2009ZX01028-002-003,2009ZX01029-001-003,2010ZX01036-001-002;the National Natural Science Foundation of China under Grant Nos. 61050002,60736012,60921002,61003064

摘　　要：The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS （Globally Asynchronous Locally Synchronous） and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson- 3B is maintained by MLMM （Multi Level Multi Mode） clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops （double-precision） or 256 GFlops （single-precision） with 40 W power consumption.The Godson-3B processor is a powerful processor designed for high performance servers including Dawning Servers. It offers significantly improved performance over previous Godson-3 series CPUs by incorporating eight CPU cores and vector computing units. It contains 582.6 M transistors within 300 mm2 area in 65 nm technology and is implemented in parallel with full hierarchical design flows. In Godson-3B, advanced clock distribution mechanisms including GALS （Globally Asynchronous Locally Synchronous） and clock mesh are adopted to obtain an OCV tolerable clock network. Custom-designed de-skew modules are also implemented to afford further latency balance after fabrication. The power reduction of Godson- 3B is maintained by MLMM （Multi Level Multi Mode） clock gating and multi-threshold-voltage cells substitution schemes. The highest frequency of Godson-3B is 1.05 GHz and the peak performance is 128 GFlops （double-precision） or 256 GFlops （single-precision） with 40 W power consumption.

关 键 词：physical implementation hierarchical design flow GALS clock mesh low power 

分 类 号：TP332[自动化与计算机技术—计算机系统结构] TP311.13[自动化与计算机技术—计算机科学与技术]