无线显示适配器的ME结构设计与FPGA实现  

ME architecture design and FPGA implementation for wireless display adapter

作　　者：安西平[1] 杨大利[1] 

机构地区：[1]北京信息科技大学计算机学院,北京100101

出　　处：《北京信息科技大学学报（自然科学版）》2011年第2期77-81,共5页Journal of Beijing Information Science and Technology University

基　　金：北京市属市管高等学校人才强教计划资助项目(PHR201007131)

摘　　要：为保证无线显示适配器对视频进行实时压缩编码,提出了一种基于全搜索块匹配算法的运动估计硬件结构,并在FPGA上实现。结构采用二维processsing element(PE)阵列,设计的搜索窗寄存器阵列可获得搜素范围数据最高的复用率,经过优化的PE单元结构减少了对硬件资源的需求。实验结果显示,系统运算速度快,PE利用率高,在工作主频35.6 MHz下,能实时完成1 280×720@30fps视频编码,可用于无线显示适配器的编码端。To guarantee the real-time video compression of the wireless display adapter,a motion estimation hardware architecture based on a full-search block-matching algorithm is proposed.A 2-D PE array is adopted to implement the structure and the design is synthesized and implemented on FPGA.The designed search window register array can obtain the highest rate of data re-use and PE cell structure is optimized to reduce the demand on hardware resources.Experimental results show that this architecture has fast processing speed and high PE efficiency.It can achieve real-time processing of 1 280×720 @ 30fps video at 35.6MHz,so it can be used for wireless display adapter encoder.

关 键 词：运动估计 全搜索算法 硬件结构 现场可编程门阵列 

分 类 号：TN919.81[电子电信—通信与信息系统]