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作 者:CHEN YingMei WANG ZhiGong & ZHANG Li
机构地区:[1]Institute of RF-& OE-ICs, Southeast University, Nanjing 210096, China
出 处:《Science China(Information Sciences)》2011年第6期1293-1299,共7页中国科学(信息科学)(英文版)
基 金:supported by the National Natural Science Foundation of China(Grant No.60976029)
摘 要:A high-scale integrated optical receiver including a preamplifier, a limiting amplfiaer, a clock anO data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 p,m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-topeak jitter of the recovered 625 MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recomnaendation G.958. In response to 2.5 Gb/s PRBS input data (223-1), the recovered and frequency divided 625 MHz clock has a phase noise of -83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).A high-scale integrated optical receiver including a preamplifier, a limiting amplfiaer, a clock anO data recovery (CDR) block, and a 1:4 demultiplexer (DEMUX) has been realized in a 0.25 p,m CMOS technology. Using the loop parameter optimization method and the low-jitter circuit design technique, the rms and peak-topeak jitter of the recovered 625 MHz clock are 9.4 and 46.3 ps, respectively, which meet the jitter specifications stipulated in ITU-T recomnaendation G.958. In response to 2.5 Gb/s PRBS input data (223-1), the recovered and frequency divided 625 MHz clock has a phase noise of -83.8 dBc/Hz at 20 kHz offset and the 2.5 Gb/s PRBS data has been demultiplexed into four 625 Mb/s data. The power dissipation is only 0.3 W under a single 3.3 V supply (excluding output buffers).
关 键 词:optical receiver JITTER PREAMPLIFIER limiting amplifier clock and data recovery DEMULTIPLEXER
分 类 号:TN791[电子电信—电路与系统] TP368.1[自动化与计算机技术—计算机系统结构]
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