AES算法中模逆运算电路设计与实现  

Design and Implementation of Modular Inversion Circuits in AES Algorithm

作　　者：程桂花[1] 齐学梅[2] 罗永龙[1] 

机构地区：[1]安徽师范大学数学计算机科学学院,安徽芜湖241000 [2]安徽师范大学网络与信息安全工程技术研究中心,安徽芜湖241000

出　　处：《小型微型计算机系统》2011年第6期1240-1244,共5页Journal of Chinese Computer Systems

基　　金：国家自然基金项目(60703071)资助;安徽省优秀青年科技基金项目(08040106806)资助;安徽省自然科学基金项目(070412043)资助

摘　　要：AES算法中字节替换和轮密钥扩展都需使用模逆运算.模逆运算是AES算法中最复杂的运算,也是AES算法中最关键的模块之一.本文分析二进制扩展的欧几里德算法,基于该算法使用Verilog HDL设计模逆运算电路,通过FPGA实现模逆运算.电路选用优先权编码器、比较器和移位寄存器等基本逻辑部件组成,使得两个多项式次数的计算、比较、相减和多项式系数的移位操作并行进行,加速模逆运算的过程.硬件实现模逆运算具有高效、快速的特点,对AES算法的硬件实现具有实际价值.In AES Algorithm,Modular inversion is used in Substitute Bytes and round key expansion,it is important and complex processing of AES.In this paper,Extended Euclidean algorithm for binary polynomials is analyzed and propounded,base on this algorithm,we designed a modular inversion circuit in Verilog HDL,modular inversion is realized by FPGA.The circuit is composed of basic logic circuit,including priority encoder,comparer and shift register,degree of polynomial computation and compare and subtraction and polynomial coefficient of displacement can be be paralleled for speeding up the process of die for the inverse operation.Modular inversion with Hardware Implementation is high efficiency and high speed,these circuits hold practical value to AES Algorithm with Hardware Implementation.

关 键 词：AES算法 模逆运算 二进制扩展的欧几里德算法 硬件设计 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]