分布实时仿真中的时钟硬同步研究  

Study of Clock Hard-synchronization in Distributed Real-time Simulation

作　　者：陈勇[1] 姚新宇[1] 潘玉林[2] 唐小凤 

机构地区：[1]国防科技大学机电工程与自动化学院,长沙410073 [2]徐州工程兵指挥学院,徐州221004 [3]后后勤科学研究所,北京100071

出　　处：《系统仿真学报》2011年第6期1146-1150,共5页Journal of System Simulation

摘　　要：为了满足分布实时仿真在苛刻实时层上对时钟同步的高精度要求,提出了一种时钟硬同步方案,利用FPGA硬件电路跟踪锁定外部1PPS时钟信号,生成高精度高分辨率的本地时钟。重点解决了本地晶振频率校正,外时钟的毛刺剔除、丢失补发及重新锁定,同步误差分析及补偿等问题。实验结果表明,时钟硬同步作为物理层同步技术,克服了传统软同步的协议开销及网络传输延时的不确定性,能够实现微秒级同步精度。To reach high clock-synchronization precision at rigorous real-time level for Distributed Real-Time Simulation,a method of clock hard-synchronization was proposed.This method used FPGA hardware circuit to track and lock external 1PPS clock signal,then created local clock of high precision and resolution.Local oscillator frequency calibration,glitch elimination,lost clock regeneration,and clock relocking problems were well solved.Also,error analysis and compensation was presented.The results show that hard-synchronization,as a technology based on physical layer overcoming protocol consumption and transfer delay uncertainty,could achieve microsecond range precision.

关 键 词：时钟硬同步 分布实时仿真 频率校正 FPGA 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]