基于SoC和软硬件协同处理的可重构JPEG2000实现  

Reconfigurable Implementation of JPEG2000 Based on SOC and Software/Hardware Cooperation

作　　者：王怡倢[1] 李会方[1] 罗鹏[1] 吉作约子[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710129

出　　处：《微电子学与计算机》2011年第6期74-78,83,共6页Microelectronics & Computer

摘　　要：提出一种基于SOC、具有可重构功能的JPEG2000软硬件协同实现方案.重点分析并实现了一种提升9/7、5/3算法的统一流水线结构.对于标准算法中的彩色变换、内容模型生成模块、Tier1编码和MQ编码器采用硬件加速处理,并对图像预处理单元、Tier2编码和系统控制功能则采用软件在NiosⅡ嵌入式系统上实现.最后采用以Altera公司的EP3C25F672作为核心芯片的开发系统,对该算法进行了软、硬件仿真,结果证明采用软、硬件协同处理,能有效地克服JPEG2000在实际应用中存在的速度和灵活性之间的瓶颈,具有计算效率高和芯片利用率高等一系列优点.In the paper the reconfigurable solution of implementation of JPEG2000 algorithm based on SOC and software/harware Cooperation is presented,and combined pipeline architecture for the 5-3 and 9-7 lifting wavelet transforms is designed.The module such as,color space transform,context formation,tier1 encoder and arithmetic encoder have been realized with our proposed architectures on FPGA to improve speed.The functions of image preprocessing,tier2 encoder and system control etc.have been finished with Nios II embeded processor software.Finally,The proposed scheme is verified with FPGA software/hardware platform based on EP3C25F672 chip of Altera Company.The experimental results of simulation with the cooperation of software and hardware show that the proposed method can effectually solve the problem about the bottleneck between coding speed and flexibility,and take the advantages both improving compression efficiency and saving chip area.

关 键 词：JPEG2000 图像压缩 现场可编程门阵列 提升小波变换 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]