一种高性能低功耗的运动估计的设计  

Design of a high-performance and low-power motion estimation

作　　者：郑吉君[1] 

机构地区：[1]上海交通大学微电子学院,上海200240

出　　处：《信息技术》2011年第5期84-86,90,共4页Information Technology

摘　　要：基于运动估计的全搜索算法,人们提出了有预处理的脉动阵列硬件结构,相较于无功耗处理的原始脉动阵列减少了12.3%。在此基础上,进一步根据逻辑产生门控时钟以及停止寄存器链对电路进行管理,取得了69.2%的功耗节省。A pretreatment systolic array hardware architecture is proposed based on full-search algorithm of motion estimation.This architecture reduces 12.3% compared with non-power processing primitive systolic array.Based on this,futher manages circuit according to the logic producing gating clock as well as stopping register chain,and achieves 69.2% power savings.

关 键 词：全搜索算法 脉动阵列 预处理 门控时钟 

分 类 号：TN911.73[电子电信—通信与信息系统]