A 4 GS/s 4 bit ADC with 3.8 GHz analog bandwidth in GaAs HBT technology  

作　　者：吴旦昱 周磊 郭建楠 刘新宇 金智 陈建武 

机构地区：[1]Institute of Microelectronics,Chinese Academy of Sciences [2]Key Laboratory of Microelectronics Devices & Integrated Technology,Institute of Microelectronics,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2011年第6期104-110,共7页半导体学报（英文版）

基　　金：Project supported by the State Key Development Program for Basic Research of China(No2010CB327505)

摘　　要：An ultra-wideband 4 GS/s 4 bit analog-to-digital converter（ADC）which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth（ERBW）of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones（DC-6 GHz）.The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm^2.An ultra-wideband 4 GS/s 4 bit analog-to-digital converter（ADC）which is fabricated in 2-level interconnect, 1.4μm InGaP/GaAs HBT technology is presented.The ADC has a-3 dB analog bandwidth of 3.8 GHz and an effective resolution bandwidth（ERBW）of 2.6 GHz.The ADC adopts folding-interpolating architecture to minimize its size and complexity.A novel bit synchronization circuit is used in the coarse quantizer to eliminate the glitch codes of the ADC.The measurement results show that the chip achieves larger than 3.4 ENOBs with an input frequency band of DC-2.6 GHz and larger than 3.0 ENOBs within DC-4GHz at 4 GS/s.It has 3.49 ENOBs when increasing input power by 4 dB at 6.001 GHz of input.That indicates that the ADC has the ability of sampling signals from 1st to 3rd Nyquist zones（DC-6 GHz）.The measured DNL and INL are both less than±0.15 LSB. The ADC consumes power of 1.98 W and occupies a total area of 1.45×1.45 mm^2.

关 键 词：ADC FOLDING interpolating GaAs ultra-wide-band synchronization 

分 类 号：TN792[电子电信—电路与系统] TN911.6