用于H.264编解码的面向HDTV应用的动态可重构多变换VLSI结构  

A Dynamic Reconfigurable H.264 Multi-Transform VLSI Architecture for HDTV Application

作　　者：洪琪[1] 曹伟[1] 童家榕[1] 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203

出　　处：《电子学报》2011年第5期1059-1063,共5页Acta Electronica Sinica

基　　金：专用集成电路与系统国家重点实验室重点课题(No.09ZD005);专用集成电路与系统国家重点实验室开放课题(No.10KF014)

摘　　要：提出了一种新的支持MPEG-4 AVC/H.264标准4×4整数变换的动态可重构结构.首先,针对4×4正反变换分别推导了两个新的二维直接信号流图.进而设计了一个面向HDTV应用的动态可重构多变换结构.该结构无需转置寄存器且计算单元仅需16个加法器(减法器).采用0.18μm CMOS工艺实现了该电路结构.结果表明,最高工作频率可达200MHz,电路规模仅为5140门,最大功耗仅为15.64mW.在100MHz的时钟频率下工作,该电路即可实时处理HDTV 1080P的高质量视频序列.对比现有结构,在HDTV应用中,该结构在面积和功耗方面优势明显.This paper presents a new dynamic reconfigurable architecture of the 4×4 integer transforms for the MPEG-4 AVC /H.264 standard.Two novel 2-D direct signal flow graphs of the 4×4 forward and inverse transforms for H.264 are proposed.A dynamic reconfigurable multi-transform architecture without using transpose memory is proposed on the basis of the new SFGs.There are 16 adders（subtractors） in it.Our design is implemented with 0.18um CMOS technology.The optimum clock frequency of the circuit for the multiple transforms is 200MHz which achieves 800Mpixels/s data throughput rate with the area cost of 5140 gates and the power dissipation of 15.64 mW.Under a clock frequency of 100 Mhz,the architecture allows the real-time processing of HDTV 1080P.Compared with the existing architectures,our design is more efficient in terms of area and power dissipation for HDTV application.

关 键 词：H.264 整数变换 动态可重构结构 信号流图 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]