二维提升小波的VLSI结构设计及FPGA验证  

Design of VLSI Architecture of 2-D Lifting Wavelet and FPGA Verification

作　　者：孟伟[1,2] 金龙旭[1] 韩双丽[1] 

机构地区：[1]中国科学院长春光学精密机械与物理研究所,吉林长春130033 [2]中国科学院研究生院,北京100039

出　　处：《液晶与显示》2011年第3期404-408,共5页Chinese Journal of Liquid Crystals and Displays

摘　　要：针对JPEG2000中小波变换的硬件实现占用资源量大、速度慢等问题,提出了一种有效的二维小波硬件实现模型。该模型采用流水线并行结构,即对图像中各行像素进行流水线处理的同时,对小波分解的各级采用并行结构处理。这样的结构提高了小波变换的处理速度,实现了实时处理,节省了硬件的片上存储及外部存储资源。用FPGA对此模型进行验证。验证实验采用Xinlinx公司的SPARTEN-3系列芯片,对1 024×2 048的大图像进行处理,图像处理速度达到80Mpixels/s,满足实时性要求。In order to save the resource and improve the speed of wavelet transform＇s hardware realization,an effective 2-dimension wavelet transform hardware structure has been proposed.This structure used parallel pipeline architecture,each layer of wavelet transform processed by parallel while pixels processed by pipeline.And the structure can improve the speed of wavelet transform,save the on-chip and external memory resource.It had been tested on Xilinx SPARTEN-3 series FPGA by processing large image with size 1 024×2 048.Results showed the image processing speed could reach 80 Mpixel/s,meeting the real-time requirement.

关 键 词：JPGA2000 小波变换 并行结构 提升算法 

分 类 号：TN911.73[电子电信—通信与信息系统]