FPGA控制下面阵CCD时序发生器设计及硬件实现  

Design of a Driving Schedule Generator for the Area Array CCD Controlled by FPGA

作　　者：朱冰莲[1] 杜培强[1] 运明华[1] 

机构地区：[1]重庆大学通信工程学院,重庆400044

出　　处：《电子科技》2011年第6期127-130,133,共5页Electronic Science and Technology

摘　　要：在分析Sony公司ICX098BQ面阵CCD图像传感器驱动时序的基础上,对可调节曝光时间的CCD时序发生器及其硬件电路进行设计。选用FPGA器件作为硬件设计平台,使用VHDL语言对时序关系进行了硬件描述,采用Quartus Ⅱ 8.0对所设计的时序发生器进行了功能仿真,并以Altera公司的可编程逻辑器件为核心进行硬件适配。实际测试表明,所设计的驱动时序发生器能够满足面阵CCD的驱动要求,实现了设计目的。In this paper,driving timing of Sony ICX098BQ area array CCD image sensor is analyzed.CCD timing generator with adjustable exposure time and its hardware circuit are designed.FPGA is chosen as the hardware design platform,and schedule generator is described with VHDL.The designed generator successfully fulfills function simulation with Quartus II 8.0 and fit into FPGA made by Altera.Actual tests show that driving schedule generator meets the driving requirement of area array CCD and achieves the design objectives.

关 键 词：面阵CCD FPGA 时序发生器 

分 类 号：TN79[电子电信—电路与系统] TP752.2[自动化与计算机技术—检测技术与自动化装置]