双频双模导航基带芯片的静态时序分析  

Static Timing Analysis for Baseband IC in Dual-Mode/Dual-Frequency Navigation Receiver

作　　者：常江[1] 张晓林[1] 苏琳琳[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《微电子学》2011年第3期350-353,358,共5页Microelectronics

基　　金：国防科工委重大民品专项

摘　　要：针对一款双频双模导航基带芯片的ASIC设计,提出一种多异步时钟域的时序约束设计方法,并通过设置虚假路径、多周期路径和修正建立保持时间违例的方法,优化了时序。最终使芯片满足系统时序要求,通过了静态时序验证,为芯片流片提供了可靠保证。For ASIC design of baseband circuit in dual-frequency/dual-mode compatible navigation receiver,a timing constraint designation method was proposed for multiple asynchronous clock domain.The timing was optimized by setting false-path and multicycle-path,and modifying method for setup and hold time violation.The proposed designation method enabled baseband IC to satisfy timing requirements of the system and pass the static timing analysis,ensuring tape-out functions of the IC.

关 键 词：双频双模 基带芯片 静态时序验证 时序优化 

分 类 号：TN402[电子电信—微电子学与固体电子学]