区域填充扫描线算法的硬件设计与实现  

The Hardware Design and Implementation of Area Filling Scanline Algorithm

作　　者：李平[1] 韩俊刚[1] 李自迪[1] 杨婷婷[1] 

机构地区：[1]西安邮电学院,西安710061

出　　处：《微计算机信息》2011年第6期124-125,71,共3页Control & Automation

摘　　要：在图形处理器(GPU)的研究中,提高图形加速器的描绘速度,特别是提高区域填充的效率是一个关键技术。采用软件实现区域填充,速度慢,限制了图形加速器效率的提高。本文采用一种改进的区域填充扫描线算法,设计了具体的硬件实现方法,并将其应用于一个完整的2D图形加速器系统,提高了加速器的效率,最终在Altera的cycloneII系列开发板上进行了验证。With the research and development of Graphics Processing Unit（GPU）,how to improve the rendering speed of graphics accelerator has become a hot topic.The area filling,as a key technology in graphics accelerators,is traditionally based on software implementation.It restricts the development of graphics accelerators greatly.This paper takes an improved region filling scan line algorithm and gives the specific design and implementation of hardware.Then it is applied to a complete 2D graphics accelerator system,and verified by using Altera＇s cyclone II development board.

关 键 词：图形加速器 扫描线算法 FPGA 

分 类 号：TP391[自动化与计算机技术—计算机应用技术]