高速广义多载波解调的低成本硬件优化设计  

Low-cost hardware optimization design for high-speed GMC demodulation

作　　者：熊何锐[1] 郝学飞[1] 胡国荣[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《西安电子科技大学学报》2011年第3期169-174,共6页Journal of Xidian University

摘　　要：针对广义多载波解调,设计了一种输出符合多相滤波器串行输入的512点流水线结构逆快速傅里叶变换处理器,从而避免了系统中额外的数据存储,减少了系统总体的硬件开销和运算延时.处理器基本运算单元采用一种输入正序、输出正序的新型基23单路延时本地反馈结构.经过三级基本单元和一级深度为64的缓存后,最终输出为按逆快速傅里叶变换计算结果以因子8抽取的序列.在具体实现中,还提出了一种提取公因值的方法来优化旋转因子的存储.该处理器用FPGA验证,相比传统基23单路延时反馈结构和基8前向反馈结构,存储资源可分别减少30%和67%,并且比单路延时反馈结构输出延时减少约43%.Based on GMC （ Generalized Multi-carrier） demodulation, a 512 point pipelined IFFT processor is proposed, whose output sequence is consistent with the input sequence of the polyphase filter, thus avoiding the extra data storage and reducing the hardware cost and latency of the whole system. The processor takes a new radix 23 SDLF （Single-path Delay Locally Feedback） architecture as the basic operating unit, which has a sequence input and a sequence output. After three stages＇ operation and a buffer with the depth of 64, the processor＇s final output is the extraction of IFFT results by factor of 8. In the design, a method for extracting the common factor is also proposed to opimize twiddle factor storage. The verification, based on the FPGA, indicates that the proposed processor can reduce the memory size by 30% and 67% respectively, compared with the traditional radix 23 SDF （Single-path Delay Feedback） and radix 8 FF （ Feed Forward） architecture, and reduce output latency by about 43%, compared with the SDF architecture.

关 键 词：广义多载波 快速傅里叶变换 单路延时本地反馈 旋转因子 

分 类 号：TN91[电子电信—通信与信息系统]