用于网同步的数字处理智能锁相环  

Digital Processing Phase-locked Loop for Network Synchronization

作　　者：何岩[1] 

机构地区：[1]邮电部激光通信研究所

出　　处：《光通信研究》1989年第2期28-34,共7页Study on Optical Communications

摘　　要：把大规模集成电路和计算机结合,构成数字处理智能锁相环(DP-PLL)。DP-PLL依靠存贮程序控制获得较好的同步性能,可以抑制很低频率的相位抖动及具有一定抗输入信号扰动的能力,是实现网同步的理想部件。本文主要论述DP-PLL系统的结构、设计方法和实验结果。By combining LSI with computers, an intelligent phase-locked loop using digital processing (DP-PLL) can be created. It features a excellent performance of synchronization by a stored program control, and it is an ideal component for network synchronization, because it is able to suppress the ex(?)remely low frequency jittering and can tolerate disturbances of input signal. This paper mainly describes the structure and the design method of the DPPLL. The results of the experiment and the test of the DP-PPL are also presented.

关 键 词：网同步 锁相环 DP-PLL 数字处理 

分 类 号：TN911.8[电子电信—通信与信息系统]