降低电荷泵锁相环频率合成器的杂散分析  

Analysis of Reduction of CPPLL Frequency Synthesizers' Spur

作　　者：耿波[1] 高玉良[2] 管亮中[1] 

机构地区：[1]空军雷达学院研究生管理大队,武汉430019 [2]空军雷达学院五系,武汉430019

出　　处：《空军雷达学院学报》2011年第3期196-198,共3页Journal of Air Force Radar Academy

摘　　要：为了改善锁相环频率合成器的杂散,分析了电荷泵锁相环频率合成器杂散的表征形式以及产生的原因,并提出了5种降低杂散的方法,最后通过ADS软件进行了仿真.仿真结果表明:在改变参数为原先的50%的情况下,减小分频比来降低杂散的效果最为明显,可以减小3.823 dB,而减少环路极点则相对弱一些,只减小了1.605 dB.在工程实践中借鉴这些方法可设计出符合杂散需求的频率合成器.In order to reduce the spur of the frequency synthesizer,this paper expounds the spur expression of the charge-pump phase-locked loop（CPPLL） frequency synthesizers and the causes,then proposes five methods of reducing the spur,and finally performs the simulation using ADS software.Simulation results show that the effect of lowering spur can be super when reducing the frequency division ratio,which can reduce by 3.823 dB,while the effect is less strong relatively when reducing the number of loop poles,only lowering by 1.605 dB.Therefore,the approaches proposed can be a useful reference for designing the frequency synthesizers that meet the demand of spur in engineering.

关 键 词：电荷泵锁相环 频率合成器 杂散分析 

分 类 号：TN74[电子电信—电路与系统]