应用于ΣΔADC的抽取滤波器的设计与实现  

Design and Implementation of a Decimation Filter for ΣΔADC

作　　者：李海龙[1] 黑勇[1] 乔树山[1] 范军[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学与计算机》2011年第7期72-75,81,共5页Microelectronics & Computer

摘　　要：介绍了一种应用于ΣΔADC的抽取滤波器的设计和电路实现方法.通过对传统设计方法的分析,提出了一种可以节省10%硬件利用率的改进方法,同时提出了一种适用于半带滤波器的串并联结构,与传统的半带滤波器相比能够提高50%的硬件利用效率.在面积、速度和功耗的折衷的情况下,灵活应用CSD、CSE和多相分解结构,在0.18μm下实现了0.59 mm2的16位数字抽取滤波器.该滤波器与不应用串并联结构的滤波器相比能够节省18%左右的芯片面积.A kind of design method and hardware realization about the digital decimation filter used for high resolution ΣΔ ADC is introduced.An improved design method which has 10% hardware saving compared to tradition architecture is proposed.With a new structure named series-parallel structure which is used in half-band filter,the last stage of the decimation filter will has 50% hardware saving.In the trade off between area,power consumption and speed,with the methods of CSD（canonic signed digit）,CSE（common sub-expression elimination）,Poly-phase Decomposition and the new series-parallel structure proposed here,we implemented a low power and area decimation filter.The filter whose area is 0.59mm^2 is implemented in 0.18μm CMOS process and has 18% less hardware.

关 键 词：ΣΔADC 抽取滤波器 串联并联结构 

分 类 号：TN713.7[电子电信—电路与系统]