遗传算法的FPGA硬件实现  

Hardware implementation of genetic algorithm based on FPGA

作　　者：周艳聪[1,2] 顾军华[3] 董永峰[3] 刘恩海[3] 

机构地区：[1]河北工业大学电气工程学院,天津300130 [2]天津商业大学信息工程学院,天津300134 [3]河北工业大学计算机科学与软件学院,天津300130

出　　处：《计算机工程与应用》2011年第20期9-13,16,共6页Computer Engineering and Applications

基　　金：国家自然科学基金(No.60872161);河北省自然科学基金(No.F2010000142);科技人员服务企业行动(No.2009GJA20014);天津商业大学校青年培育基金(No.090112)~~

摘　　要：针对遗传算法软件实现速度慢、效率低的缺点,提出了便于算法实现的串行和流水线两种硬件实现方案。详细描述了设计方案,选择算子、交叉变异算子结构,种群以及适应度的存储和流水线结构,并在流水线中引入并行机制。利用函数极值和旅行商问题分别对方案的资源耗费、运行速度的有效性进行了验证。实验结果显示,这两种硬件实现方法结构简单,资源耗费少,运算速度和运行效率较软件实现大大提高,运行速度平均提升2～3个数量级,为算法在一些实时性要求较高的场合得到应用提供了良好基础。To overcome the shortcoming of low speed and low efficiency of genetic algorithm＇s software implementation, two hardware implementation schemes of serial and pipelining realization are put forward.The overall design and structure of genetic operators ——selection, crossover and mutation,individual population and fitness memory are given.Other parallel mechanisms are also added to the pipelining structure.The optimal solution of function and classical travel sales problem are used to verify the effect of the schemes on resource consumption and running speed.The experimental results show that the schemes have simple structure, low resource consumption,higher running speed and efficiency than software＇s implementation. On average the running speed can be advanced 2 to 3 orders.It sets a good basis for the application of genetic algorithm on real time and high speed system.

关 键 词：遗传算法 现场可编程门阵列 流水线 旅行商问题 全局优化 

分 类 号：TP301[自动化与计算机技术—计算机系统结构]