基于FPGA的PCM30/32路系统信号同步数字复接设计  

Design of Signal Synchronous Digital Multiplexing for PCM30/32-channel System Based on FPGA

作　　者：张华伟[1] 宗瑞良[1] 

机构地区：[1]西北工业大学电子信息学院,陕西西安710129

出　　处：《现代电子技术》2011年第13期49-52,共4页Modern Electronics Technique

摘　　要：在现代数字通信系统中,为了扩大信道的传输容量提高信号传输效率,常采用数字复接的技术。在分析了PCM30/32路系统基群信号帧结构的基础上,以EDA综合仿真设计软件QuartusⅡ8.0为开发平台,利用Verilog HDL硬件描述语言进行系统建模,设计了一种基于FPGA的同步数字信号复接系统。经过对系统的功能仿真测试及综合布局布线分析,验证了输入/输出的逻辑关系,实现了系统中在发送端进行数字复接和接收端同步分解还原的设计要求,功能稳定可靠。In modern digital communication systems, multiplexing technology is extensively employed, so as to increase transmission efficiency by augmenting channel capacity. On the basis of analysis of primary group signal frame structure of PCM30/32-channel system, a FPGA based synchronous digital multiplexing system is designed, which takes EDA composite simulation design software Quartus Ⅱ 8.0 as the development platform and performs modeling with Verilog HDL. Through simulations and analyses on functionality and routing, the correctness of the logic relationship between inputs and outputs is verified. The designed system is robust and implements the design requirements of multiplexing and demultiplexing signals synchronously at the transmitting end and the receiving end respectively.

关 键 词：FPGA 数字通信 数字复接 帧同步 

分 类 号：TN914.3[电子电信—通信与信息系统]