A 5-Gbit/s monolithically-integrated low-power clock recovery circuit in 0.18-μm CMOS  

5-Gbit/s 0.18-μm CMOS单片集成低功耗时钟恢复电路设计(英文)

作　　者：张长春[1] 王志功[1] 施思[1] 潘海仙[2] 郭宇峰[1] 黄继伟[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,南京210096 [2]东南大学生物电子学国家重点实验室,南京210096

出　　处：《Journal of Southeast University(English Edition)》2011年第2期136-139,共4页东南大学学报（英文版）

基　　金：The National High Technology Research and Development Program of China (863 Program)(No. 2007AA01Z2a5);the National Natural Science Foundation of China (No. 60806027,61076073);Specialized Research Fund for the Doctoral Program of Higher Education (No.20090092120012)

摘　　要：In order to make a 10 Gbit/s 2：1 half-rate multiplexer operate without external clocks, a 5 Gbit/s clock recovery （CR） circuit is needed to extract the desired clock from one input data. For the CR circuit, a 3-stage ring voltage-controlled oscillator （VCO） is employed to avoid an unreliable startup of a 2-stage VCO and a low oscillation frequency of a 4-stage VCO. A phase frequency detector （PFD） is used to expand the pull-in range to meet the wide tuning range of a VCO required by process-voltage-temperature （PVT） variation. SMIC 0. 18-μm CMOS technology is adopted and the core area is 170 μm ×270 μm. Measurements show that, under a 1.8 V supply voltage, it consumes only about 90 mW, and has an input sensitivity of less than 25 mV, an output single-ended swing of above 300 mV, a phase noise of - 114 dBc/Hz at 1 MHz offset and a pull-in range of 1 GHz.为了使一个10Gbit/s2∶1半速率复接器电路能够在无外部提供时钟的环境中工作,需要一个5Gbit/s时钟恢复电路从一路输入数据中提取出所需时钟.该时钟恢复电路采用3级环形压控振荡器,以克服2级振荡器存在的起振不可靠和4级振荡器振荡频率低的问题;采用鉴频鉴相器来增加牵引范围,以适应由于工艺、电压及温度偏差等原因而导致的压控振荡器的宽调谐范围;采用SMIC 0.18-μm CMOS工艺,核心电路面积为170μm×270μm.测试表明:在1.8V电压下,该电路功耗大约为90mW,输入灵敏度低于25mV,输出摆幅大于300mV,且具有-114dBc/Hz@1MHz的相位噪声和1GHz牵引范围.

关 键 词：clock recovery phase frequency detector voltagecontrolled oscillator phase noise 

分 类 号：N913.7[自然科学总论]