通用型SPI总线的IP设计与实现  

Design and Implementation of IP core for universal SPI bus

作　　者：张斌 刘宇 荣金峰 

机构地区：[1]西安深亚电子公司,陕西西安710061

出　　处：《中国集成电路》2011年第7期43-47,共5页China lntegrated Circuit

摘　　要：相对于并行总线,串行总线具有结构简单的优点。近年来人们对系统功能和性能的需求不断地增长,使得处理器需要的外设越来越多。这时串行总线的优点就逐渐显现出来,因此应用的范围也越来越广。本文根据业界通用的SPI标准介绍了一种通用型SPI总线的IP设计与实现方法,采用Verilog-HDL语言完成了电路设计,并用FPGA验证了设计的可行性,并最终使得该设计作为一个完整独立的IP核成功地应用于一系列产品的设计中。Compare with parallel buses,serial buses have its own advantages,the structure of integrated circuit is much more simpler.Recently,Along with the increasing requirement of the function and the performance of device,the number of periphery equipment of CPU is becoming more and more larger.Under this background,serial buses＇ advantage gradually becomes more important,thus,its application margin becomes wider and wider.In this thesis,according to the usual standard of SPI in the field of IC,a method to design and realize IP core of a universal SPI buses is introduced and coded in Verilog-HDL,at the same time the feasibility of our method through FPGA is validated,and finally,this core has been used as an independent IP core in serials ASIC product successfully.

关 键 词：SPI总线 VERILOG-HDL FPGA ASIC 

分 类 号：TN402[电子电信—微电子学与固体电子学]