无线传感网射频芯片中4.8GHz低功耗压控振荡器设计  

Design of 4.8 GHz low power voltage-controlled oscillator for WSN RF chip

作　　者：樊祥宁[1] 曾军[1] 李斌[1] 朱薇薇[1] 陈晓光[1] 

机构地区：[1]东南大学射频与光电集成电路研究所,江苏南京210096

出　　处：《江苏大学学报（自然科学版）》2011年第4期433-437,共5页Journal of Jiangsu University：Natural Science Edition

基　　金：国家"863"计划项目(2007AA01Z2a7)

摘　　要：为满足无线传感网射频收发芯片中频率综合器的应用需求,采用TSMC 0.18μm RF CMOS工艺设计并实现了一个4.8 GHz低功耗LC压控振荡器.电路核心采用电流源偏置的互补差分负阻LC振荡器结构以及3 bit开关电容阵列,输出采用共源级缓冲.给出了电路设计,对噪声抑制进行了分析,并在Cadence环境下完成了版图设计,版图面积为700μm×900μm.在电源电压为1.8V条件下进行了后仿真,并采用2组SSGSS及1组三针直流探针完成了流片验证和芯片测试.结果表明:电路的后仿真调谐范围大于25%,能够有效地补偿工艺角偏差;在载波频率为4.8 GHz处,后仿真相位噪声为-126.8 dBc/Hz@3 MHz.实际测试中,电路的调谐范围为24%,在应用要求的3 MHz频偏处,相位噪声达到-121.12 dBc/Hz,核心电路工作电流仅为2 mA.In order to meet the application requirements of frequency synthesizer for wireless sensor network（WSN） front-end,a 4.8 GHz LC voltage-controlled oscillator（VCO） was designed and implemented based on TSMC 0.18 μm RF CMOS process.The core circuit was biased by current,and complementary differential negative resistance LC oscillator structure was adopted with a three-bit switch capacitor array.Common source structure was adopted as the output buffer.Circuit design was given,and noise restriction was analyzed in detail.The chip layout was designed in Cadence with 700 μm×900 μm pad.Simulation was completed under 1.8 V supply voltage.Two SSGSS probes and a three-pin DC probe were used for chip verification and measurement.The results show that the tuning range of post-simulation can achieve more than 25%,which can perfectly compensate the frequency offset due to process corners.The phase noise of post-simulation is-126.8 dBc/Hz@3 MHz for the carrier of 4.8 GHz.In actual chip detection,the tuning range is 24%,and the phase noise of-121.12 dBc/Hz is obtained at 3 MHz offset with core circuit operating current of only 2 mA.

关 键 词：无线传感网 压控振荡器 开关电容阵列 相位噪声 低功耗 

分 类 号：TN4[电子电信—微电子学与固体电子学]