一种面积优化的内插滤波器的设计及实现  

Design and implementation of area-efficient interpolation filter

作　　者：李晶[1] 吴晓波[1] 赵津晨[1] 

机构地区：[1]浙江大学超大规模集成电路设计研究所,浙江杭州310027

出　　处：《机电工程》2011年第7期872-875,共4页Journal of Mechanical & Electrical Engineering

基　　金：国家自然科学基金资助项目(60906012)

摘　　要：为节省芯片面积,设计并实现了一种面积优化的内插滤波器,该滤波器适用于Sigma-Delta音频数模转换器。采用级联多级半带滤波器加采样保持电路的系统结构以降低硬件复杂度。同时为了减少硬件开销,对半带滤波器的结构进行了改进。实现时采用了正则符号编码(CSD)以进一步减少芯片面积。通过Matlab仿真得到了其滤波器系数,经FPGA平台验证了其功能。滤波器采用TSMC 0.18μm CMOS工艺实现,核心芯片面积为0.34 mm2。测试结果表明,芯片达到了设计指标,并且在面积上有一定的优势。Aiming at saving the chip area , an area-efficient interpolation filter for Sigma-Delta audio digital-to-analog convener（DAC） was designed and implemented. In an effort to reduce the complexity of the system, the interpolation filter was comprised of cascade halfband fil- ters and a sample-and-hold stage. An improved structure of halfband filter was proposed to achieve the hardware efficiency. The canonic signed digital （CSD） representation was used to further reduce the area of the interpolation fiher. The coefficients were attained from the Matlab simulation, and the correctness of the design was verified in FPGA. The cell area of the interpolation filter is 0.34 mm2 in TSMC 0. 18 p,m CMOS process. The experimental results indicate that the proposed interpolation filter accords with the design specification, exhibi- ting area efficiency.

关 键 词：数模转换器 内插滤波器 半带滤波器 正则符号编码 

分 类 号：TP391[自动化与计算机技术—计算机应用技术] TN713.7[自动化与计算机技术—计算机科学与技术]