基于FPGA可重构快速密码芯片设计  

Design of Fast Reconfigurable Cipher Chip Based on FPGA

作　　者：李可长[1] 

机构地区：[1]柳州职业技术学院,广西柳州545006

出　　处：《计算机测量与控制》2011年第7期1665-1667,共3页Computer Measurement &Control

基　　金：广西教育厅科研基金项目(200911LX492)

摘　　要：为提高密码芯片的应用效益,提出了一种基于FPGA可重构的密码芯片实现方法。该方法打破了传统了一类密码芯片采用一种设计方案的模式,通过对FPGA的重构设计,能够动态地实现多种不同计算特征的密码算法芯片。同时对最基础的乘法运算和加法运算,设计了细粒度流水的加速策略。该方案能够重构实现DES、AES、RSA、椭圆曲线密码算法等典型密码算法,对600M的数据文件加密测试,DES的加速比为2.8,AES的加速比为3.6。In order to enhance the application benefit of the password chip,has proposed one kind of the cipher chip realization method with reconfigurable technical based on FPGA.This method broke the pattern that the traditional kind of cipher chip design with one kind of proposal,through to the FPGA reconfigurable design,could dynamic realize many kinds of different computation characteristic crypto-algorithm chip,enhanced the design flexibility greatly.Meanwhile regarding the most foundation units which inluding the multiply operation and the additive operation,has designed the fine grain pipeline acceleration strategy.The cipher chip designed in this paper can reconfigurable realizes DES,AES,RSA,the elliptic curve crypto-algorithm and so on typical crypto-algorithm,Has taken the test with 600M data file,the DES acceleration ratio is the 2.8,AES acceleration ratio is 3.6.

关 键 词：可重构 密码芯片 FPGA 细粒度流水 逻辑单元 

分 类 号：TN791[电子电信—电路与系统]