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作 者:李秀圣[1]
机构地区:[1]潍坊学院,山东潍坊261061
出 处:《潍坊学院学报》2011年第4期5-8,共4页Journal of Weifang University
摘 要:介绍了一种基于现场可编程逻辑阵列和数字信号处理器协同作业的高速图像处理嵌入式系统。借助于单片双口RAM,设计了一种新颖的数据传输结构,并利用乒乓技术实现对实时高速图像数据的缓冲。整个系统的工作流程在FPGA和DSP的分工及协作下完成,这比使用单片DSP建立的处理系统性能提高25%左右。该系统具有可重构性,方便其它算法在该系统上实现。A high-efficient image processing embedded system which is based on the field programmable gate array and high-speed digital signal processor was designed in this paper.With a dual-port RAM,a novel data transmission structure was designed,and ping-pong technique was used to implement the buffering of the high-speed real-time image data.The total working process was completed in FPGA and DSP's division and cooperation,so it is 25% higher than the processing system based on the single DSP in performance.Other algorithms can be transplanted to the system easily for the system's reconfigurability characteristic.
关 键 词:FPGA DSP JPEG 双口RAM 图像压缩
分 类 号:TP274.2[自动化与计算机技术—检测技术与自动化装置]
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