群路CPC收发器的硬件实现  

Implementation of a Group CPC Transceiver Based on Hardware

作　　者：赵志远[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所

出　　处：《计算机与网络》2011年第11期54-57,共4页Computer & Network

摘　　要：在对循环排列码字(CPC)的特点进行分析之后,以某通信专网的群路接口为例,介绍了一种群路CPC收发器的硬件电路设计方案,给出了CPC译码表的生成算法,着重对电路的模块划分、功能及实现方法、寄存器设计及使用方式进行了详细说明,简要分析了该电路的检测性能。该设计采用现场可编程逻辑器件(FPGA)实现,资源占用较低,具有很好的移植性,简单修改后即可用于类似接口,是一种较为通用的CPC收发电路。After analyzing the features of CPC code, this paper introduces a hardware design method of a group CPC transceiver based on a group interface of one special communication networks. It presents a function to generate the CPC decoding table, and gives emphasis to module division, function implementing and register design. The decoding performance of the circuit is briefly analyzed. This design is implemented on FPGA chips, uses fewer chip resources and is easy to migrate, and it can be used in similar interface after simple changes. It＇s a common CPC transceiver.

关 键 词：CPC FPGA 随路信令 比特交织 

分 类 号：TN859[电子电信—信息与通信工程]