并行DSP系统软件调试器设计与实现  

Implementation of a Parallel DSP System Debugger

作　　者：吴琼之[1] 南方[1] 张峰[1] 

机构地区：[1]北京理工大学信息与电子学院,北京100081

出　　处：《北京理工大学学报》2011年第7期855-858,共4页Transactions of Beijing Institute of Technology

摘　　要：针对数字信号处理器(DSP)构成的专用并行处理系统的软件调试存在较多困难这一问题,提出了系统级调试的概念,在层次化总线硬件架构模型的基础上,讨论了系统软件调试的基本方法和任务,并采取层次化数据结构、静态符号表自动生成、可扩展底层接口等关键技术实现了一种专用多DSP系统调试工具.分析表明,此调试工具大大减轻了实时信号处理软件的调试工作量.For the requirement that software debugging is quite difficult for dedicate parallel processing system consisting by multiple digital signal processor （DSP）, concept of system-level debugging was proposed. The basic task and method of system-level debugging was discussed based on the hierarchical shared bus hardware structure model. A system level software debugger was designed and implemented with some key technology including hierarchical data structure, static symbol table auto-generation and extendable low level interface. This debugger makes it easy for system and global level debugging of large DSP processing array.

关 键 词：并行处理 信号处理机 软件调试 

分 类 号：TP338[自动化与计算机技术—计算机系统结构]