基于FPGA的DDS+DPLL跳频信号源设计  

Design of DDS+PLL Frequency Hopping Signal Source Based on FPGA

作　　者：杨红[1] 李海[1] 隆行[1] 

机构地区：[1]电子科技大学成都学院微电子技术系,四川成都611731

出　　处：《现代电子技术》2011年第15期101-104,共4页Modern Electronics Technique

摘　　要：针对跳频通信系统有固有噪声的特点,结合DDS+DPLL高分辨率、高频率捷变速度的优点,并采用Altera公司的Quartus-Ⅱ_10.1软件进行设计综合,提出了一种新型的跳频信号源。结果表明,该设计中DPLL时钟可达到120MHz,性能较高,而仅使用了30个LUT和18个触发器,占用资源很少。Since the frequency hopping（FH） communication system has the inherent noise characteristics,a new FH signal source is proposed in combination with high-resolution high-frequency agility advantages of DDS＋DPLL and Quartus-Ⅱ_10.1 software of Altera Company for design.Only 30 LUTs and 18 triggers are used in the design.The simulation results show that the designed DPLL clock is up to 120 MHz and its performance is high.

关 键 词：数字鉴相器 滤波器 数控振荡器 DPLL 

分 类 号：TN911-34[电子电信—通信与信息系统]