ARINC 659总线收发器的设计与优化  

Design and Optimization of ARINC 659 Transceiver

作　　者：邵刚[1] 田泽[1] 韩炜[1] 

机构地区：[1]中国航空工业集团公司西安计算技术研究所,陕西西安710068

出　　处：《计算机技术与发展》2011年第8期39-41,45,共4页Computer Technology and Development

基　　金：国家"十二五"微电子预研项目(513080106)

摘　　要：ARINC 659总线是航空电子产品里使用较多的一种wire-OR总线结构。文中介绍了一款为8通道的ARINC 659总线优化的收发器的设计和优化,首先研究了ARINC 659背板应用的物理效应、负载、驱动能力和传输延迟等特性,并综合考虑BTL电平标准和wire-OR总线结构及ARINC 659总线负载和应用实际,使用0.35μm BiCmos工艺进行了8通道的ARINC 659总线收发器芯片的设计和优化。通过测试表明,ARINC 659总线端与TTL端的收发正常,交流参数符合IEEE1194.1,ARINC 659物理层的定义。综合测试结果文中所述的收发器功能正确,可用于ARINC 659物理层的收发。ARINC 659 bus is a kind of wired-OR bus which was widely used in aeronautic electric equipment.In the article a 8 channels ARINC 659 transceiver was designed and optimized.Firstly,the backplane environment was investigated with respect to physical effect,load and transition characteristic.Secondly,the BTL standard,the bus structure and the application factor are taking into account in this design.Finally,the chip was made with 0.35μm BiComs process with 8 channels in a chip.The test results show that the transmit functions are realized,DC,AC parameter fit IEEE 1194.1 and ARINC 659 physical layer definition.In conclusion,the design work fulfills all the functions which were designed,the chip can be used as ARINC 659 physical layer transceiver with low bit error rate.

关 键 词：ARINC 659 BTL 收发器 IEEE 1194.1 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]