一种wallace树压缩器硬件结构的实现  

Realization of wallace tree style compressor hardware structure

作　　者：管幸福[1] 余宁梅[1] 路伟[1] 

机构地区：[1]西安理工大学自动化与信息工程学院,西安710048

出　　处：《计算机工程与应用》2011年第23期76-78,83,共4页Computer Engineering and Applications

摘　　要：设计了一种用于32位浮点乘法器尾数乘部分的wallace树压缩器的硬件结构实现方法,通过3-2和4-2压缩的混合搭配,构成一种新的wallace树压缩器,采用verilog硬件描述语言实现RTL级代码的编写,并使用VCS进行功能仿真,然后在SMIC0.13μm的工艺下,用synopsys DC进行逻辑综合、优化。结果表明,这种压缩器在部分积的压缩过程中,有效地提高了运算速度,并在很大程度上减小了硬件实现面积。This paper describes a hardware structure realization method of wallace tree compressor used for mantissa product of 32-bit float-point multiplying unit.Mixed with 3-2 and 4-2 compressor,wallace tree compressor adopts hardware description language to realize the RTL code writing,and makes use of VCS for functional simulation and synopsys DC for logic synthesis and optimization under SMIC0.13 μm processes.The results show that this kind of compressor benefits the increasing of arithmetic speed during compression process of partial product and reducing of hardware realization area to a large extent.

关 键 词：3-2压缩器 4-2压缩器 wallace树压缩器 

分 类 号：TP27[自动化与计算机技术—检测技术与自动化装置]