2.125～3.125GHz高速CMOS锁相环电路设计  

Design of a 2.125-3.125 GHz CMOS Phase-Locked Loop

作　　者：邢立冬[1,2] 蒋林[1] 

机构地区：[1]西安邮电学院电子工程学院,西安710121 [2]西安电子科技大学微电子学院,西安710071

出　　处：《微电子学》2011年第4期510-514,519,共6页Microelectronics

基　　金：陕西省教育厅科研计划项目(2010JK827);西安邮电学院中青年基金资助项目(ZL2009-24)

摘　　要：针对数模混合结构的电荷泵锁相环电路,建立了系统的数学模型,确定了电荷泵锁相环的系统参数,提出一种能够有效消除时钟馈通、电荷注入等非理想特性影响,并具有良好电流匹配特性的电荷泵电路,以及一种中心频率可调的压控振荡器电路。电路采用SMIC 0.18μm CMOS工艺模型,使用Spectre进行仿真。结果显示,整个锁相环系统的功耗约为40 mW,输出时钟信号峰-峰值抖动为21 ps@2.5 GHz,单边带相位噪声在5 MHz频偏处为-105 dBc/Hz。A 2.125-3.125 GHz mixed-signal charge pump phase-locked loop（CPPLL） was designed and implemented.Mathematical model of PLL was established based on theoretical analysis and technical specification.Parameters of the PLL were discussed in detail.A charge pump circuit with good current matching characteristics and a VCO circuit with its center frequency adjustable were proposed.Based on SMIC＇s 0.18 μm CMOS model,the circuit was simulated using Spectre simulator.Results from simulation showed that the PLL had a power consumption of 40 mW,an output clock peak-to-peak jitter of 21 ps and a single side-band（SSB） phase noise of-105 dBc/Hz at 5 MHz offset.

关 键 词：数模混合电路 电荷泵 锁相环 峰-峰值抖动 

分 类 号：TN495[电子电信—微电子学与固体电子学]